Modern computers have seen skyrocketing clock speeds which have allowed faster instruction execution and increased work throughput. Memory systems coupled to these computer systems have also increased in speed and complexity due to numerous system memory configurations, resulting from different memory attributes choices such as size, parity, non-parity, synchronous, asynchronous, etc. The task of identifying a particular computer system's memory configuration presents a daunting task.
One prior art technique uses switches or jumpers to define memory size, location, or other memory attributes. This approach allows the computer system to retain the memory attributes when power to the system is turned-off. The technique, nevertheless, is cumbersome because of the requirement to reconfigure the switches or jumpers due to changes in memory modules having different memory attributes. In addition, a user making the memory module changes must have some degree of mechanical aptitude due to the requirement to remove the covers of the computer system, identify and replace a desired memory module.
Another prior art technique discloses the use of hard wiring a two-bit identification (ID) value on a memory card to allow identification of the vendor, size and speed of a particular dynamic random access memory (DRAM) module. The two-bit identification value is hard wired either to ground or voltage for each of four cross bar switches assigned to each dynamic memory module. During a DRAM refresh cycle, the two-bit identification value is gated to a memory controller through the cross bar switches to form an identification byte. The technique thus eliminates the need to change jumpers or switches when a memory card is changed in the computer system. However, a user is still unable to directly determine the presence and identity of the memory module. The technique not only requires four cross bar switches for each memory module on the card, but also requires a memory controller to examine the two-bit values on each cross bar switch and concatenate the values into an information byte. In addition, the hard-wired two-bit identification values must be done when the card is manufactured which limits any future changes to the cards.
Yet another prior art technique discloses a programmable memory address decoder for a computer system where a static random access memory (SRAM) is programmed by a processor using embedded firmware and programmable logic arrays (PLA). The programmable memory address decoder is capable of storing memory attribute information for a plurality of dynamic single inline memory modules (SIMMs) in its SRAM. This memory attribute information conveys whether single-sided or double-sided SIMMs are inserted into one of four banks, or whether the SIMMs should be used as an external cache. However, this technique must rely on the firmware stored in the memory controller to determine what memory modules are populated in the computer system. In addition, the memory controller is incapable of reading directly from the populated memories themselves to determine the presence and identity of a second level cache memory module.
The problems of detecting and identifying memory modules is exacerbated by the use of n-th level cache memories. An n-th level cache is n-1 levels away from a Central Processor Unit (CPU). A first level cache (also called an internal, primary, level-1 or L1 cache) is usually built into the processor chip itself, while second level caches (also called external, secondary, level-2 or L2 cache) and higher level caches are usually outside the processor chip. Some computer systems may have levels beyond L2, but generally, each cache level away from the processor (e.g., larger values of n) is typically larger, but slower then levels closer to the processor.
Consequently, it would be desirable to provide a technique for directly detecting the presence and identity of second level cache memory modules in a computer system.